Carrier tracking circuit and method including dual numerically controlled oscillators and feedforward phase correction coefficient

ABSTRACT

A carrier tracking circuit includes a first phase adjustment circuit coupled to an input of a delay element and a second phase adjustment circuit coupled to an output of the delay element. A phase correction circuit is coupled to output of the delay element is operable to generate a phase adjustment value based upon a data symbol output from the delay element. The phase correction circuit includes a double phase correction circuit to prevent double application of the same phase adjustment value to a symbol by both the first and second phase adjustment circuits. The carrier tracking circuit may be used in OFDM communications systems with each data symbol being an OFDM symbol and with the delay element being an FFT. The carrier tracker circuit also may include a feed forward circuit for correcting the phase error of a given data symbol using a phase error generated from that symbol.

PRIORITY CLAIM

This application claims priority from U.S. Provisional PatentApplication No. 60/449,042 filed Feb. 21, 2003, which is incorporatedherein by reference.

TECHNICAL FIELD

The present invention relates generally to communications systems andmore specifically to the correction of frequency offsets betweenreceivers and transmitters in such communications systems.

BACKGROUND OF THE INVENTION

In a typical communications system, a transmitter encodes data to betransmitted and this encoded data is used to modulate a carrier signalwhich is transmitted over a communications channel to a receiver. Thereceiver demodulates the received carrier signal to obtain the encodeddata and thereafter decodes the encoded data to obtain the original datasent by the transmitter. The type of modulation utilized in thecommunications system indicates the parameter of the carrier signal thatis varied to encode the data onto the carrier signal, such as amplitude,frequency, or phase modulation and combinations thereof, as will beunderstood by those skilled in the art. One such modulation technique isknown as frequency division multiplexing which utilize, instead of asingle carrier signal, a number of subcarrier signals at differentfrequencies that are simultaneously communicated over the communicationschannel. With frequency division multiplexing a portion of the databeing transmitted is modulated onto each of the subcarrier signals.

A frequency division multiplexing modulation technique known asorthogonal frequency division multiplexing (OFDM) has becomeincreasingly popular in recent years for use in wireless communicationssystems. This is true because the intrinsic characteristics of OFDMallow it to handle the most common types of distortion found in thewireless environment, such as fading of the received signal resultingfrom the transmitted signal arriving at the receiver over multiplepropagation paths due to reflections and objects present between thetransmitter and receiver. As a result, many wireless local area networks(WLANs) utilize OFDM in the form of the IEEE 802.11 family of standardsthat are more commonly referred to as “wireless fidelity” or “Wi-Fi.”

In a wireless OFDM communications system, an OFDM signal is formedthrough the summation of a number of orthogonal subcarriers, eachsubcarrier having a different frequency and itself being modulatedthrough a particular modulation technique such as quadrature amplitudemodulation (QAM). The subcarriers are orthogonal in that the dot productof each subcarrier with any of the other subcarriers is equal to zero,as will be understood by those skilled in the art. This orthogonalproperty of each subcarrier results in a frequency spectrum for eachsubcarrier that has a peak frequency component FC positioned betweenpeak frequencies f of adjacent subcarriers and that has frequency nullspositioned at the locations of these adjacent peak frequencies as shownin FIG. 1. The resulting frequency spectrums for these orthogonalsubcarriers enable each of these subcarriers to be reliably demodulatedfrom the OFDM signal, with each subcarrier thereafter being demodulatedthrough the appropriate technique, such as QAM, to retrieve theunderlying data, as will be understood by those skilled in the art.

The OFDM signal formed by the summation of these orthogonal subcarriersis typically utilized to modulate a radio frequency (RF) carrier signalwhich, in turn, is the actual signal propagated over the wirelesschannel. More specifically, a local oscillator in the transmittertypically generates the RF carrier signal and a modulation circuitmodulates this carrier signal with the OFDM signal. In the receiver, alocal oscillator generates a signal that is applied to a mixer alongwith the received modulated RF carrier signal to thereby remove thecarrier signal portion and provide the original OFDM signal in thereceiver.

Although OFDM is well suited for use in wireless communications systemsas previously mentioned, there are nonetheless types of distortion thatmust be compensated for with OFDM just as with any modulation technique.One such type of distortion is frequency-offset distortion that resultsfrom a difference between the frequency of an oscillator or RF signalgenerated by the local oscillator in the OFDM transmitter and thefrequency of the RF signal generated by the local oscillator in the OFDMreceiver. Such a frequency offset results in the OFDM signal having afrequency offset relative the original OFDM signal in the transmitter,and this type of distortion can adversely affect the performance of thesystem.

To overcome the problem of frequency offset, the receiver typicallyincludes a carrier tracking circuit that adjusts the frequency of thelocal oscillator in the receiver to match that of the local oscillatorin the transmitter as closely as possible. FIG. 2 is a functional blockdiagram illustrating a conventional carrier tracking circuit 200contained in an OFDM receiver for adjusting the frequency of a signalgenerated by a numerically controlled oscillator (NCO) 202 in thereceiver. Although not shown in FIG. 2, the modulated RF signal receivedfrom the transmitter (not shown) is first demodulated or “downconverted” using a local oscillator signal from a local oscillator (notshown) contained in the receiver. As previously mentioned, ideally thefrequency of the local oscillator signal in the receiver is the same asthat of the local oscillator in the transmitter that was modulated bythe OFDM signal.

Once the RF signal has been down converted to provide the OFDM signal inthe OFDM receiver, this OFDM signal is sampled to generate a pluralityof samples r(n). The NCO 202 then adjusts the phases of each of thesesamples to compensate for a frequency offset between the localoscillator in the receiver and the local oscillator in the transmitter,as will now be explained in more detail. Note that OFDM signal in thereceiver generated after down conversion is not identical to the OFDMsignal in transmitter if there is a frequency offset between the localoscillator in the transmitter and the local oscillator in the receiver.Such a frequency offset results in a linearly cumulative phase error foreach sample r(n) of the OFDM signal, as will be understood by thoseskilled in the art. As result, if the first sample r(n) has a phaseerror θ_(err) then the second sample will have a phase offset 2θ_(err),and so on for each sample. Thus, each sample may be viewed as having aphase offset of n times θ_(err) where n indicates the sample number.

The NCO 202 receives a phase adjustment value PHADJ from a loop filter204, with the PHADJ value having a value corresponding to theincremental amount by which the phase of each of the samples r(n) is tobe adjusted. A summation circuit 206 adds the PHADJ value with a phaseincrement value PHINC output from a delay circuit 208 to generate anaccumulated phase value PHAC that is also input to the delay circuit.The delay circuit 208 outputs the PHAC value on its input as the PHINCvalue on its output a sample delay time τ_(s) later. A second summationcircuit 210 subtracts the PHINC value from a phase of the sample r(n) togenerate a phase-corrected sample {dot over (r)}(n) that is supplied toa fast Fourier transform (FFT) circuit 212. The sample delay time τ_(s)corresponds to time between which the samples r(n) are applied to thesummation circuit 210.

Once the FFT 212 receives a required number N of the phase-correctedinput samples {dot over (r)}(n), the FFT executes a fast Fouriertransform algorithm to calculate a set of complex frequency componentsR(1)-R(N). The fast Fourier algorithm is a discrete Fourier transformalgorithm that greatly reduces the number of computations required tocompute the discrete Fourier transform of the input signal correspondingto the N samples {dot over (r)}(n). Each of the frequency componentsR(1)-R(N) is a complex number giving a magnitude and phase for acorresponding sinusoidal component of the input signal in a givenfrequency range or “bin” of the FFT 212. Recall that according toFourier transform theory, a signal may be represented as a summation ofsinusoids of different frequencies and varying magnitudes and phases.The frequency components R(1)-R(N) generated by the FFT 212 define themagnitudes and phases of N sinusoids, each at a corresponding frequency,which, when summed together yield the input signal corresponding to thephase-corrected samples {dot over (r)}(n). In the just describedoperation of the FFT 212, a single OFDM symbol that encodescorresponding data is represented by the N phase-corrected input samples{dot over (r)}(n).

The carrier tracking circuit 200 further includes a phase errorestimator 214 that generates an estimated phase error value EPHE fromthe frequency components R(1)-R(N) output by the FFT 212. The estimator214 typically utilizes frequency components R(1)-R(N) having known phasevalues to calculate the EPHE value. For example, in an OFDM system thatcomplies with the IEEE 802.11 standard, N=64 so that the FFT 212includes 64 bins and outputs the frequency components R(1)-R(64) in therespective bins. Of these 64 bins, four bins contain what are typicallyreferred to as “pilot tones” having known amplitude and phase values.The phase error estimator 214 determines the estimated phase error valueEPHE from phase values of the frequency components R(1)-R(64)corresponding to the pilot tones. The loop filter 204 generates thephase adjustment value PHADJ having a value that is a fraction of theEPHE value from the estimator 214. The loop filter 204 feeds back only afraction of the EPHE value in the form of the PHADJ signal to improvethe stability of the circuit 200 since the NCO 202 utilizes the PHADJvalue to ultimately adjust the phase of each of the samples r(n), aswill be appreciated by those skilled in the art.

In operation, assume that the delay circuit 208 initially outputs a zerovalue for the PHINC value and that the samples r(n) corresponding to afirst OFDM symbol are sequentially applied to the summation circuit 210.Also assume the PHADJ value from the loop filter 204 has an initialdefault value PHADJ-DF and that the first sample r(1) of the first OFDMsymbol is applied to the summation circuit 210 within the delay timeτ_(s) of the delay circuit 208 after the PHADJ-DF value is initiallyinput to the delay circuit. At this point the delay circuit 208 outputsa zero for the PHINC value when the r(1) sample is applied to thesummation circuit 210 since the PHADJ-DF value is not yet output fromthe delay circuit. The summation circuit 210 therefore subtracts zerofrom the phase of the first sample r(1) and in this way does not adjustthe phase value of this sample. Thus, the summation circuit 210 outputsthe sample r(n) with no phase correction as the phase-corrected sample{dot over (r)}(1) that is supplied to the FFT 212.

After the delay time τ_(s), the delay circuit 208 outputs the PHADJ-DFvalue as the phase increment value PHINC that is applied to thesummation circuit 210. This occurs at the same time the second sampler(2) of the current OFDM symbol is applied to the summation circuit 210,causing the circuit 210 to subtract the PHINC value from the phase ofthis sample. The summation circuit 210 at this point outputs thephase-corrected sample {dot over (r)}(2) to the FFT 212, with thisphase-corrected sample corresponding to the sample r(2) having the PHINCvalue subtracted from it phase. Note that while the summation circuit210 is adjusting the phase of the sample r(2), the output of the delaycircuit 208 is also fed back and applied to the summation circuit 206.As a result, the summation circuit 206 sums the PHINC value, which isequal to PHADJ-DF at this point, and the PHADJ-DF value from the loopfilter 204 and outputs a value of 2×PHADJ-DF as the accumulated phasevalue PHAC that is supplied to the delay circuit 208.

After the delay time τ_(s), the delay circuit 208 outputs the value2×PHADJ-DF as the PHINC value that is supplied to the summation circuit210, which occurs at the same time the sample r(3) is being applied tothe summation circuit. The summation circuit 210 therefore subtracts thevalue 2×PHADJ-DF from the phase of the sample r(3) to thereby supply thephase-corrected sample {dot over (r)}(3) to the FFT 212. The NCO 202continues operating in this manner for all samples r(n) in the firstOFDM symbol, and in this way linearly increases the phase offset PHINCthat the circuit 210 subtracts from the phase of the sequential samplesr(1), r(2), r(3), and so on to r(N). Accordingly, the phase offset ofzero is subtracted from the sample r(1), the phase offset subtractedfrom sample r(2) is PHADJ-DF, phase offset subtracted from sample r(3)is 2×PHADJ-DF, phase offset subtracted from sample r(4) is 3×PHADJ-DF,and so on until the phase offset of (N−1)×PHADJ-DF is subtracted fromthe final sample r(N) of the OFDM symbol.

Once the summation circuit 210 supplies the phase-corrected sample {dotover (r)}(N) to the FFT 212, the FFT calculates the correspondingfrequency components R(1)-R(N) for this first OFDM symbol from thephase-corrected samples {dot over (r)}(1)-{dot over (r)}(N). The FFT 210outputs these components R(1)-R(N) from the carrier tracking circuit 200to other circuitry (not shown) in the OFDM receiver for processing. Atthe same time, the phase error estimator 214 generates a new estimatedphase error value EPHE from the ones of these components R(1)-R(N)corresponding to the pilot tones in the OFDM symbol. As previouslymentioned, in an IEEE 802.11 system each OFDM symbol includes four pilottones having known phase values and the estimator 214 compares theactual to the expected phase values for these pilot tones to generatefour phase error components, and then takes the average of these fourphase error components to generate the EPHE value.

In response to this new EPHE value from the estimator 214, the loopfilter 204 takes a fraction of this value to generate the new PHADJvalue that is applied to the summation circuit 206. The summationcircuit 206 sums this new PHADJ value with the current PHINC value togenerate a new PHAC value, which is thereafter output from the delaycircuit 208 the delay time τ_(s) when the first sample r(1) of the nextOFDM symbol is supplied to the summation circuit 210. This is true ifthe delay through the FFT 212 is relatively short such that this updatedvalue for the EPHE may be fed back to the NCO 202 in time to apply thisupdated value to the samples r(n) of the next OFDM symbol. In reality,however, the delay through the FFT 212 may be several symbols long suchthat, eventually, the EPHE calculated for a given OFDM symbol, saysymbol X, is used to correct the phases of samples r(n) in an OFDMsymbol X+Y where Y is the number of symbol delays through the FFT.

Because the delay time through the FFT 212 can be relatively long, thecarrier tracking circuit 200 is always using the estimated phase errorEPHE from a prior OFDM symbol to correct the phase errors of samplesr(n) for a subsequent OFDM symbol. In fact the FFT 212 may have apipelined architecture in which several OFDM symbols are applied to theFFT before the frequency components R(1)-R(64) corresponding to a firstOFDM symbol are output by the FFT, as alluded to above. In thissituation, the phase error EPHE from an initial OFDM symbol is used tocorrect the phase errors of samples r(n) for an OFDM symbol that issampled several symbols after that initial symbol. This may result ininaccurate phase adjustments of the samples r(n) in the subsequent OFDMsymbol due to the intervening linearly cumulative phase error of thesamples.

It should also be noted that in the circuit 200 the phase errorestimator 214 is used to estimate an average phase error EPHE that isthen used to adjust the phases of the samples r(n) of a subsequent OFDMsymbol. Thus, if this average phase error EPHE is considered to be thephase error at the middle one of the samples, which is r(32) in the IEEE802.11 example currently being used, then an additional 32 samples willhave occurred since this estimated phase error value. As a result, thephase adjustment of the NCO 202 will adjust the phases of the samplesr(n) of the next OFDM symbol based upon the PHADJ value which wasgenerated from this average phase error value EPHE. This means that theNCO 202 will adjust the phase of the first sample r(n) of the next OFDMsymbol by the PHADJ value corresponding to the middle sample r(32) ofthe prior OFDM symbol, even though thirty two more samples have occurredbetween this middle sample and the first sample of the next symbol.Recall, the phase shift error from one sample r(n) to another islinearly cumulative due to the frequency offset, and thus the use ofthis average phase error value PHADJ does not take into account thelinearly accumulated phase error between sample location where the errorwas estimated and the current sample. Note that while the carriertracking circuit 200 includes the FFT 212 and is discussed as being partof an OFDM receiver, the concepts discussed above apply generally toother types of systems as well. More specifically, the concepts apply toany carrier tracking or other similar circuit where an element (e.g.,the FFT 212 in FIG. 2) introduces a delay between the NCO 202 and anoutput of the element from which a phase error is estimated.

There is a need for a carrier tracking circuit and method that morequickly and more accurately correct for phase errors of a received OFDMor other type of signal due to frequency offset distortion.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a carrier trackingcircuit includes a first phase adjustment circuit coupled to an input ofa delay element and a second phase adjustment circuit coupled to anoutput of the delay element. A phase correction circuit is coupled tooutput of the delay element is operable to generate a phase adjustmentvalue based upon a data symbol output from the delay element. The phasecorrection circuit includes a double phase correction circuit to preventdouble application of the same phase adjustment value to a symbol byboth the first and second phase adjustment circuits. The carriertracking circuit may be used in OFDM communications systems with eachdata symbol being an OFDM symbol and with the delay element being anFFT. The carrier tracker circuit also may include a feed forward circuitfor correcting the phase error of a given data symbol using a phaseerror generated from that symbol.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing the magnitudes of frequency components for anumber of orthogonal subcarriers in an OFDM communications system.

FIG. 2 is a functional block diagram of a conventional carrier trackingcircuit contained in an OFDM receiver.

FIG. 3 is a functional block diagram of a carrier tracking circuitincluding dual numerically controlled oscillators and a feed forwardphase coefficient for correcting frequency offset errors according toone embodiment of the present invention.

FIG. 4 is a graph showing the operation of the intrasymbol step phasecompensation circuit of Figure.

FIG. 5 is a functional block diagram of an OFDM communications systemincluding an OFDM receiver containing the carrier tracking circuit ofFIG. 3 according to one embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 3 is a functional block diagram of a carrier tracking circuit 300including a first numerically controlled oscillator (NCO) 302 foradjusting the phase of the samples r(n) of an OFDM symbol prior to thosesamples being input to an FFT 304. The carrier tracking circuit 300further includes a second NCO 306 for quickly adjusting the phases ofthe frequency components R(1)-R(64) that are output by the FFT 304 foran OFDM symbol using an estimated phase error EPHE for the immediatelypreceding OFDM symbol. Moreover, the carrier tracking circuit 300 alsoincludes a feed forward phase correction circuit 308 for immediatelyadjusting the phase errors of the frequency components R(1)-R(64) of agiven OFDM symbol using a scaled estimate of the phase error EPHE forthat symbol. The NCO 302 further includes an intrasymbol step phasecompensation circuit 310 that generates a step increment in the phaseadjustment applied to the samples r(n) by the NCO 302 to compensate forthe additional phase error that occurs between the middle sample r(32)of the OFDM symbol for which the estimated phase error EPHE iscalculated and the linearly cumulative phase error resulting from theadditional 32 samples r(33)-r(64) of the symbol that occur prior to thefirst sample of the next OFDM symbol, as will be described in moredetail below along with all of the components and overall operation ofthe carrier tracking circuit 300.

In the following description, certain details are set forth inconjunction with the described embodiments of the present invention toprovide a sufficient understanding of the invention. One skilled in theart will appreciate, however, that the invention may be practicedwithout these particular details. Furthermore, one skilled in the artwill appreciate that the example embodiments described below do notlimit the scope of the present invention, and will also understand thatvarious modifications, equivalents, and combinations of the disclosedembodiments and components of such embodiments are within the scope ofthe present invention. Embodiments including fewer than all thecomponents of any of the respective described embodiments may also bewithin the scope of the present invention although not expresslydescribed in detail below. Finally, the operation of well knowncomponents and/or processes has not been shown or described in detailbelow to avoid unnecessarily obscuring the present invention.

In the carrier tracking circuit 300, the NCO 302 includes a summationcircuit 312, a delay circuit 314, and a summation circuit 316 thatoperate individually and in combination in the same way as thecomponents 206, 208, and 210 previously described with reference to thecarrier tracking circuit 200 of FIG. 2. The same is true of a summationcircuit 318, delay circuit 320 and summation circuit 322 contained inthe second NCO 306. Note that some of the values such as the accumulatedphase value PHAC1 and phase increment value PHINC1 include 1's toindicate that they are associated with the first NCO 302 while thecorresponding values PHAC2 and PHINC2 include 2's to indicate that theyare associated with the second NCO 306. A phase error estimator 324 andloop filter 326 operate in the same way as the corresponding components214 and 204 previously described with reference to the tracking circuit200 of FIG. 2.

The intrasymbol step phase compensation circuit 310 receives the phaseadjustment value PHADJ from the loop filter 326 through a delay circuit328, with the value output from a delay circuit being designated PHADJ1.The delay circuit 328 delays the application of a new PHADJ value to thestep phase compensation circuit 310 in the form of the PHADJ1 value sothat this phase adjustment value is not applied until the start or firstsample r(1) of the next OFDM symbol. The step phase compensation circuit310 includes a delay circuit 330, a summation circuit 332, a multiplier334 that receives a phase scale factor PSF, and a summation circuit 336that operate in combination to initially increase the PHADJ1 value by astep phase value STEPH determined by the phase scale factor PSF. Thisadjustment to the PHADJ1 value is to compensate for the linearlycumulative phase error that has occurred between the middle sample r(32)of the OFDM symbol from which the PHADJ1 value was generated and thefirst sample of the next OFDM symbol r(1), as will be described in moredetail below.

The step phase compensation circuit 310 generates a step phaseadjustment value STPHADJ in response to the STEPH and PHADJ1 values. TheSTPHADJ value sets the PHINC1 value applied to the first sample r(1) ofan OFDM symbol to an initial value and operates in combination with thecomponents 312-314 to thereafter linearly increment this initial STPHADJvalue by the value PHADJ1 for each subsequent sample r(n) of the OFDMsymbol being demodulated.

The carrier tracking circuit 300 further includes a delay circuit 338that supplies the PHADJ value from the loop filter 326 to a first inputof a summation circuit 340 which also receives the PHADJ value directlyon a second input. The summation circuit 340 subtracts the value outputfrom the delay circuit 338 from the PHADJ value to thereby provide aphase adjustment value PHADJ2 to the second NCO 306. The delay circuit338 has a delay D_(n) which delays application of the PHADJ value to thesummation circuit 340 until an OFDM symbol has had its correspondingsamples r(t) adjusted by the NCO 302 and the corresponding frequencycomponents R(1)-R(N) have been output from the FFT 304. The function ofthe delay circuit 338 and summation circuit 340 is to subtract out thePHADJ value from the phase adjustment performed by the second NCO 306 onfrequency components R(1)-R(N) of an OFDM symbol that has already hadthe phases of its samples r(1)-r(n) adjusted by the NCO 202 using thissame PHADJ value, as will be described in more detail below. Thisprevents erroneous double phase adjustment for the same OFDM symbolusing the same PHADJ value both before and after the FFT 304. Thus, thedelay circuit 338 and summation circuit 340 may be collectively referredto as a double phase correction circuit. As will be explained in moredetail below, it should be noted that the second NCO 306 adjusts each ofthe phase values of the frequency components R(1)-R(N) output from theFFT 304 by the same amount in response to a given PHADJ value.

Finally, the carrier tracking circuit 300 includes the feed forwardphase correction circuit 308 that adjusts the phase values of thefrequency components R(1)-R(N) for a given OFDM symbol using theestimated phase error EPHE for that symbol. More specifically, the feedforward phase correction circuit 308 includes a multiplier 342 thatreceives the EPHE value from the phase error estimator 324 and alsoreceives a feed forward scale factor FFSF. In response to the FFSFfactor, the multiplier 342 generates a feed forward offset value FFO bymultiplying the EPHE value times the FFSF factor. The FFO value isapplied to a summation circuit 344 that receives phase correctedfrequency components R′(1)-R′(N) from the NCO 206, and subtracts the FFOvalue from each of these components to generate feed forward phasecorrected frequency components R″(1)-R″(N) that are output from thetracking circuit 300 to other circuitry (not shown) in the OFDMreceiver.

The overall operation of the carrier tracking circuit 300 will now bedescribed in more detail. Initially, assume the phase error estimator324 outputs a default EPHE value of zero and the loop filter 326similarly generates a default PHADJ value of zero in response to thisdefault EPHE value. Also, assume the values initially output from eachof the delay circuits 314, 320, 328, 330, and 338 are all zero, and thatthe phase scale factor value PSF equals 32 and the feed forward scalefactor is 0.75 (i.e., less then one). Note the PSF value is assumed tobe 32 merely for simplicity's sake, and may be different to take intoaccount cyclic prefixes present in real OFDM symbols. For example, inIEEE 802.11 each symbol may include sixteen samples as the cyclic prefixand thus in this situation the PSF factor would equal 32+16=48 so as toaccount for the cumulative phase shift from the middle of a first OFDMsymbol to the first sample of the next OFDM symbol. Also assume that thereceived OFDM symbols conform to the IEEE 802.11 standards so that eachsymbol is modulated on 64 subcarriers and that 64 samples r(1)-r(64) foreach symbol are applied to the FFT 304 which, in turn, generates thecorresponding 64 frequency components R(1)-R(64) from these samples.

Initially, the samples r(n) corresponding to a first OFDM symbol areapplied to the NCO 302. In response the assumed zero default value forthe PHADJ1 value, the step phase compensation circuit 310 outputs a zeroSTPHADJ value to the summation circuit 312. This is true because at thispoint the output of the delay circuit 330 is zero and thus the summationcircuit 332 applies a zero value to the multiplier 324, which multipliesthis zero value by the PSF value to thereby generate a zero STEPH value.The summation circuit 336 sums the zero STEPH value with the zero PHADJ1value to provide the zero STPHADJ value. This zero STPHADJ value resultsin the summation circuit 312 and delay circuit 314 operating incombination to maintain the value of PHINC1 at zero for all the samplesr(n) in the first OFDM symbol. As a result, the NCO 302 does not adjustthe phase of any of the samples r(n) of the first OFDM symbol, meaningthat the phase corrected samples {dot over (r)}(n) equal the samplesr(n) for this first OFDM symbol.

Once the phase-corrected samples {dot over (r)}(1)-{dot over (r)}(64)have been output to the FFT 304, the FFT generates the correspondingfrequency components R(1)-R(64). Because of the assumed zero defaultvalue of the PHADJ value, the second NCO 306 receives the frequencycomponents R(1)-R(64) and does not adjust the phase of any of thecomponents, meaning the phase corrected frequency components R′(1)-R′(N)output from the summation circuit 322 are equal to the componentsR(1)-R(64). This is true because zero PHADJ value is applied to thesummation circuit 340 which also receives a zero value from the delaycircuit 338 and thus outputs a zero for the PHADJ2 value supplied to theNCO 306. In the NCO 306, the delay circuit 320 initially outputs a zerofor the PHINC2 value and thus the summation circuit 318 sums the zeroPHADJ2 and PHINC2 values and outputs a zero accumulated phase valuePHAC2 to the delay 320. Thus, as long as the PHADJ2 value is zero, thePHINC2 value will remain a zero causing the summation circuit 322 tosubtract zero phase from the phase values of each of the frequencycomponents R(1)-R(64).

The phase corrected frequency components R′(1)-R′(N) are supplied to thefeed forward phase correction circuit 308, and the summation circuit 344subtracts the FFO value from the phase of each of these components. Alsonote that at this point, the frequency components R′(1)-R′(N) areapplied to the phase error estimator 324, which uses the pilot tones inthese components to generate a new EPHE value. This new EPHE value ispresumably non-zero, and is supplied to the feed forward phasecorrection circuit 308. More specifically, the multiplier 342 receivesthe new EPHE value and the FFSF factor, which is assumed to be 0.75, andthus outputs 0.75EPHE as the FFO value. The summation circuit 344 thensubtracts this FFO value for the estimated phase error of the frequencycomponents R′(1)-R′(N) to thereby generate the feed forward phasecorrected frequency components R″(1)-R″(N) that are output form thecarrier tracking circuit 300. As seen from this description, the feedforward phase correction circuit 308 uses the estimated phase errorvalue EPHE for a given OFDM symbol to correct the correspondingfrequency components R′(1)-R′(N) of that symbol. In this way thecorrection circuit 308 immediately adjusts the phases of the componentsR′(1)-R′(N) without delay.

At this point, the new nonzero EPHE value is supplied to the loop filter326 which, in turn, develops a new nonzero PHADJ value from this EPHEvalue. Also note that at this time the samples r(n) corresponding to thesecond OFDM symbol are being input to the first NCO 302. Due to thedelay circuit 328, the new PHADJ value will not, however, be output asthe PHADJ1 value to the first NCO 302 until after the samples from thesecond OFDM symbol are applied to the first NCO. As a result, the PHADJ1value remains zero at this point and the first NCO 302 thus subtractszero PHINC1 values from the phase of each samples r(n), meaning that thephase-corrected samples {dot over (r)}(1)-{dot over (r)}(N) for thesecond OFDM symbol have zero phase correction. Once all samples {dotover (r)}(1)-{dot over (r)}(N) are supplied to the FFT 304, the FFTcalculates the FFT of these samples to generate the frequency componentsR(1)-R(N).

At this point, the delay circuit 328 outputs the PHADJ1 value that isequal to the PHADJ value previously calculated from the first OFDMsymbol. In response to the nonzero PHADJ1 value, the summation circuit332 sums the zero from the delay circuit 330 with the PHADJ1 value andthus at this point outputs the PHADJ1 value to the multiplier 334. Themultiplier 334 multiplies the PSF value times the PHADJ1 value togenerate the STEPH value. Recall, the PSF value is equal to 32 in thepresent example so that the STEPH value equals 32×PHADJ1. The summationcircuit 336 adds the STEPH value to the PHADJ1 value to generate theSTPHADJ value having a value of 33×PHADJ1. This properly accounts forthe accumulated phase error from the middle sample r(32) of the firstOFDM symbol until first sample r(1) of the third OFDM symbol (i.e.,r(32)-r(64) plus one equals 33). The STPHADJ value is input to the delaycircuit 314 which, after the delay time τ_(s), applies this value as thePHINC1 value to the summation circuit 316 to subtract this amount ofphase correction from the first sample r(n) of the third OFDM symbol.

Now that the step phase compensation circuit 310 has adjusted the phasecorrection PHINC1 that is applied to the first sample r(1) of the thirdOFDM symbol, subsequent samples r(2)-r(64) should have this initialvalue incremented by the PHADJ1 value applied to them. The compensationcircuit 310 thus removes the STEPH value after this factor has been usedto correct the first sample r(1) as follows. After the delay time of thedelay circuit 330, which would also be approximately τ_(s), the delaycircuit outputs the PHADJ1 value and thereby causes the summationcircuit 332 to apply a zero value to the multiplier 334. In response tothe zero value from the summation circuit 332, the multiplier 334multiplies the PSF value times zero and outputs a zero for the STEPHvalue. At this point, the summation circuit 336 adds the zero STEPHvalue to the PHADJ1 value and thus provides the PHADJ1 value as the stepphase adjustment value STPHADJ. The step phase compensation circuit 310maintains the STPHADJ value equal to the PHADJ value for the remainingsamples of the third OFDM symbol. The summation circuit 312, delaycircuit 314, and summation circuit 316 thereafter operate in combinationas previously described to increment the initial value of the phaseincrement PHINC1 (33×PHADJ1) by the PHADJ1 value for each subsequentsample. Thus, the PHINC1 value subtracted from the sample r(2) equals34×PHADJ1, the PHINC1 value subtracted from the sample r(3) equals35×PHADJ1, and so on. In this way, the NCO 302 utilizes the estimatedphase adjustment PHADJ1 obtained from the first OFDM symbol to adjustthe phases of the samples r(n) in the third OFDM symbol.

While the NCO 302 is adjusting the phases of the samples r(n) of thethird OFDM symbol, the second NCO 306 will utilize the same estimatedphase adjustment PHADJ from the loop filter 326 obtained from the firstOFDM symbol to adjust the phases of the frequency components R(1)-R(N)of the second OFDM symbol when output from the FFT 304, as will now beexplained in more detail. When the PHADJ value generated from the firstOFDM symbol is applied to the summation circuit 340, the delay circuit338 at this point outputs a zero causing the summation circuit 340 tooutput the PHADJ value as the PHADJ2 value that is applied to the NCO306. At this point, the summation circuit 318 adds the zero PHINC2 valueand the PHADJ2 value to provide the PHAC2 value that is equal to thePHADJ2 value. After the delay time of the delay circuit 320, which willbe approximately equal to the rate at which a frequency componentsR(1)-R(N) for respective OFDM symbols are output from the FFT 304, thedelay circuit outputs the PHINC2 value that is equal to the PHADJ2value. The summation circuit 322 then subtracts the phase PHADJ2 valuefrom the frequency components R(1)-R(N) of the second OFDM symbol outputfrom the FFT 304 to thereby generate the phase corrected frequencycomponents R′(1)-R′(N).

The delay circuit 338 and summation circuit 340 operate to prevent thedouble correction of phase values for a given OFDM symbol using the samePHADJ value from the loop filter 326. The circuits 338 and 340accomplish this by the summation circuit 340 subtracting out the alreadyused PHADJ value once the corresponding OFDM symbol is output from theFFT 304. For example, the PHADJ value generated from the first OFDMsymbol is utilized by the NCO 302 to correct the phases of the samplesr(n) of the third OFDM symbol. As a result, when the frequencycomponents R(1)-R(N) for this third OFDM symbol are output from the FFT304 the NCO 306 should not utilize the same PHADJ value to adjust thephases of the frequency components. To prevent this double correction,the delay circuit 338 outputs this PHADJ value to the summation circuit340 after the delay time D_(n). The delay time D_(n) corresponds to thetime from which a given PHADJ value is output from the loop filter 326until the time when the FFT 304 outputs the frequency componentsR(1)-R(N) of the OFDM symbol that was phase corrected by the NCO 302using this PHADJ value. Therefore, after the delay time D_(n) thefrequency components R(1)-R(N) corresponding to the third OFDM symbolare output from the NCO 302. At this same time, the delay circuit 338outputs the PHADJ value that was utilized by the NCO 302 to phasecorrect the third OFDM symbol. The summation circuit 340 then subtractsthis PHADJ value output from the delay circuit 338 from the currentPHADJ value output from the loop filter 326, which would at this pointcorrespond to a phase correction determined from the second OFDM symbol.The value from the delay circuit 338 may be designated PHADJ_(n-1) andthe value from the loop filter 326 designated PHADJ_(n) to betterdemonstrate the function of the delay circuit and summation circuit 340in subtracting out the previous phase adjustment value (PHADJ_(n-1))output from the loop filter 326 from the current value PHADJ_(n).

In the carrier tracking circuit 300, the feed forward phase correctioncircuit 308 utilizes the EPHE value for a given OFDM symbol to correctphases of the corresponding frequency components R′(1)-R′(N) of thatsymbol. Thus, the circuit 300 does not only use estimated phase errorsfrom prior OFDM symbols to correct the phase errors of subsequent OFDMsymbols. As a result, the frequency components R″(1)-R″(N) output by thecarrier tracking circuit 300 would more quickly have reduced phaseerrors notwithstanding the delay through the FFT 304. The feed forwardphase correction circuit 308 eliminates any delay in phase correctiondue to the delay through the FFT 304 and allows phase error correctionto begin immediately with the first OFDM symbol.

The carrier tracking circuit 300 also includes the second NCO 306 thatcorrects the phase values of the frequency components R(1)-R(N) of agiven OFDM symbol using a phase adjustment value PHADJ determined fromthe immediately prior OFDM symbol. Recall, in the above example thePHADJ value generated from the first OFDM symbol is used to correct thephases of the frequency components R(1)-R(N) of the second OFDM symbol.This minimizes the time lag between the estimation of a phase correctionfrom a first OFDM symbol and the subsequent OFDM symbol to which thisphase correction is applied, which would typically make the correctionsmore accurate.

The step phase compensation circuit 310 also improves the accuracy ofthe phase adjustments of the samples r(n) made by the NCO 302. Becausethe estimated phase error EPHE values from the estimator 324 representaverage values for the OFDM symbol from which they were determined, ifthese values were directly used by the NCO 302 then the linearlycumulative phase error accumulated for that symbol is not taken intoaccount. This would result in less accurate phase correction for thesamples r(n) that the NCO 302 corrects using values based upon theestimated phase error value EPHE. Once again, this improves the accuracyof the phase corrections of the carrier tracking circuit 300, which willreduce the bit error rate (BER) of OFDM symbols being transmitted to theOFDM receiver including the carrier tracking circuit.

In the circuit 300, the delays of the delay circuits 314 and 330 are thevalue τ_(s) corresponding to the time between samples r(n) applied tothe NCO 302. The delay of the delay circuit 328 is equal toapproximately the total time it takes to apply all samples r(n) to theFFT 304, and thus should be approximately N×τ_(s). The delay D_(n) ofthe delay circuit 338 is the delay from when PHADJ is output from loopfilter 326 until when the components R(1)-R(N) for an OFDM symbolcorrected by this PHADJ value are output from FFT. It should also benoted that with the carrier tracking circuit 300, the frequency of thelocal oscillator in the OFDM receiver is not compensated for directly,but instead is left alone and is compensated for via the carriertracking circuit. In another embodiment, however, the PHADJ signal couldbe fed back to control the frequency of the local oscillator thatdemodulates the modulated RF signal received by the receiver.

FIG. 4 is a graph illustrating the operation of the intrasymbol stepphase compensation circuit 310 of FIG. 3. At the top are shown threeOFDM symbols including a guard interval G that is associated with eachsymbol that is associated with each symbol to prevent intersymbolinterference, as will be appreciated by those skilled in the art. A topline indicates the linearly cumulative phase from OFDM symbol to OFDMsymbol. The second set of lines from the top indicate the phasecorrection the NCO 302 would apply without step wise compensation, whichwould be constant for each OFDM symbol since the incrementallyincreasing PHINC1 value compensates for the linearly changing cumulativephase. The third set of lines from the top show the expectedcompensation based upon the estimated phase error values EPHE. As seeneach EPHE value is effectively an estimate of the phase correction basedupon the middle sample of the OFDM symbol. Finally, the bottom set oflines indicate the one time step phase value STEPH introduced by thecompensation circuit 310 at the beginning of each OFDM symbol. FIG. 4illustrates the bump in the phase correction as the value STEPH althoughthe actual value would be STEPH+PHADJ1 as previously discussed withreference to FIG. 3. The STEPH value is thus seen to compensate for thelinearly cumulative phase error that has accumulated betweenapproximately the sample r(32) of the OFDM symbol for which the phasecorrection was determined and the first sample r(1) of the next OFDMsymbol.

Note that the phase scale factor PSF is applied to the compensationcircuit 310 by an external circuit (not shown) and has a value that isdependent upon the parameters of the OFDM symbols being received. Forexample, recall that the average phase error EPHE from the phase errorestimator 324 is considered to be the phase error at the middle one ofthe samples of an OFDM symbol, which is r(32) in the IEEE 802.11 examplebeing used herein. In this situation, an additional 32 samples will haveoccurred since this estimated phase error value EPHE was determined. Asa result, the PHADJ value from the loop filter 326, which has a valuedetermined by the EPHE value, corresponds to an estimated phase errorfor the middle sample r(32). This value should therefore be multipliedby 32 to account for the additional 32 samples r(33)-r(64) that havebeen processed since this error was estimated. The summation circuit 312then increments this value by one so that the phase adjustment appliedto the first sample r(1) of the next OFDM symbol is set to the expectedproper linearly cumulative value for this first sample.

FIG. 5 is a functional block diagram of an OFDM communications system500 including an OFDM transmitter 502 and an OFDM receiver 504containing the carrier tracking circuit 300 of FIG. 3 according to oneembodiment of the present invention. The transmitter 502 communicateswith the receiver 504 over a wireless channel 506, and includes a QAMmapping circuit 508 that receives binary data BD and maps this data intoQAM symbols. A pilot insertion circuit 510 inserts the required pilottones into the QAM symbols and applies this data to a serial-to-parallelconverter 512 which supplies a plurality of complex values in parallelto an inverse fast Fourier transform (IFFT) circuit 514.

The IFFT 514 outputs complex values representing the phase and magnitudeof the corresponding time-domain subcarrier signals. A serial-toparallel converter 518 applies the parallel complex values output fromthe IFFT 514 sequentially to a digital to analog converter 518. Thedigital to analog converter 518 generates an analog time domain OFDMsignal in response to the sequentially received digital values and thisOFDM signal is applied to an RF transmitter 520, which modulates an RFcarrier signal in response to the analog OFDM signal from the digital toanalog converter. This modulated RF carrier signal is then communicatedover the wireless channel 506 to the receiver 504.

In the receiver 504, an RF receiver 522 including a local oscillator 523demodulates the modulated RF carrier signal to generate the time domainOFDM signal. This time domain OFDM signal is applied to an analog todigital converter 524 which samples the time domain OFDM signal togenerate the phase corrected samples {dot over (r)}(n) under control ofthe carrier tracking circuit 300. The samples {dot over (r)}(n) areapplied to a serial-to-parallel converter 526 which sequentiallyreceives the samples and then applies them in parallel to an FFT 528.The FFT 528 performs a fast Fourier transform on the samples to therebygenerate the frequency components R(1)-R(N). The frequency componentsR(1)-R(N) are applied to a parallel-to-serial converter 530 whichsequentially provides the frequency components to a QAM demappingcircuit 532 that then utilizes the frequency components to map the QAMsymbols represented by the frequency components back into the originalbinary data BD.

Even though various embodiments and advantages of the present inventionhave been set forth in the foregoing description, the above disclosureis illustrative only, and changes may be made in detail and yet remainwithin the broad principles of the present invention. Moreover, thefunctions performed by components contained in the carrier trackingcircuit 300 can be combined to be performed by fewer elements, separatedand performed by more elements, or combined into different functionalblocks depending upon the actual implementation of the circuit. Forexample, the carrier tracking circuit 300 does not include theintrasymbol step phase compensation circuit 310 in another embodimentand in still a further embodiment the FFT 304 is replaced by anothercircuit that introduces a delay and the samples r(n) correspond tosamples of received signal other than an OFDM symbol. One skilled in theart will also understand circuitry and software that may be utilized toform each of the components in the carrier tracking circuit 300 and inthe OFDM communications system 500. Also one skilled in the art willrealize that other frequency analysis algorithms other than the FFT maybe used in place of the FFT 304, such as the discrete Fourier transform(DFT) or other algorithms for calculating the DFT of a signal. Thepresent invention is accordingly to be limited only by the appendedclaims.

1. A carrier tracking circuit, comprising: a first phase adjustmentcircuit having a phase adjustment input, an input sample input, and anoutput; a delay element having an input coupled to the output of thefirst phase adjustment circuit and having an output; a second phaseadjustment circuit having a component input coupled to the output of thedelay element, a phase adjustment input, and an output; a phasecorrection circuit having an input coupled to the output of the secondphase adjustment circuit and a first output coupled to the phaseadjustment input of the first phase adjustment circuit, the phasecorrection circuit including a double phase correction circuit having aninput coupled to the first output and having a second output coupled tothe phase adjustment input of the second phase adjustment circuit; and afeed forward phase correction circuit having a first control inputadapted to receive a feed forward scale factor signal and a secondcontrol input coupled to the first output of the phase correctioncircuit, and having a component input coupled to the output of thesecond phase adjustment circuit.
 2. The carrier tracking circuit ofclaim 1 wherein the phase correction circuit further comprises: a phaseestimation circuit having an input coupled to the output of the secondphase adjustment circuit and having an output; a loop filter having aninput coupled to the output of the phase estimation circuit and havingan output; and a delay circuit having an input coupled to the output ofthe loop filter and an output coupled to the phase adjustment input ofthe first phase adjustment circuit.
 3. A carrier tracking circuit,comprising: a first phase adjustment circuit adapted to receive inputsamples and operable to adjust a phase value of each input sampleresponsive to a first phase adjustment signal to thereby generate acorresponding phase-adjusted input sample, with groups of the inputsamples corresponding to sequentially received symbols; a delay elementcoupled to the first phase adjustment circuit and operable to generate agroup of output components responsive to a group of the phase-adjustedinput samples corresponding to a particular symbol; a second phaseadjustment circuit coupled to the delay component to receive the outputcomponents, the second phase adjustment circuit operable to adjust aphase value of each output component responsive to a second phaseadjustment signal to thereby generate phase-adjusted output componentscorresponding to a particular symbol; and a phase correction circuitcoupled to the first and second phase adjustment circuits, the phasecorrection circuit operable to generate the first phase adjustmentsignal having a value that is a function of the values of thephase-adjusted output components for a particular symbol, and operableto delay application of the phase adjustment signal to the first phaseadjustment circuit for approximately a first delay time at which a firstinput sample of a subsequent symbol is applied to the first phaseadjustment circuit, and the phase correction circuit further operable togenerate the second phase adjustment signal having a value that is equalto the value the first phase adjustment signal for a second delay timeand that is thereafter equal to a new value of the first phaseadjustment signal associated with a subsequent symbol minus an initialvalue of the first phase adjustment signal associated with the priorsymbol, the second delay time being equal to approximately the timebetween when the initial value of the first phase adjustment signal isgenerated and the time when the output components for a subsequentsymbol that have been phase adjusted using that initial value are outputfrom the delay element.
 4. The carrier tracking circuit of claim 3wherein the phase correction circuit further comprises a feed forwardphase correction circuit coupled to the output of the second phaseadjustment circuit, the feed forward phase correction circuit operableto adjust the phase values of the phase adjusted output components for aparticular symbol using the first phase adjustment signal generated fromthe phase adjusted output components of that symbol.
 5. The carriertracking circuit of claim 4 wherein the feed forward phase correctioncircuit generates a feed forward offset phase by multiplying the firstphase adjustment signal by a feed forward scale factor, and subtractsthe feed forward offset phase from the phase values of the phaseadjusted output components.
 6. The carrier tracking circuit of claim 5wherein the feed forward scale factor is less than one.
 7. The carriertracking circuit of claim 6 wherein the feed forward phase correctioncircuit comprises: a summation circuit that receives the phase adjustedoutput components on a first input and that receives the feed forwardoffset phase on a second input, the summation circuit operable tosubtract the offset phase from the phase values of each output componentto provide on an output feed forward phase adjusted output components;and a multiplier having a first input coupled to receive the first phaseadjustment signal, a second input coupled to receive the feed forwardscale factor, and an output coupled to the second input of the summationcircuit, the multiplier operable to multiply the first phase adjustmentsignal times the feed forward scale factor to provide the feed forwardoffset phase to the summation circuit.
 8. The carrier tracking circuitof claim 3 wherein the first phase adjustment circuit further comprisesa step phase compensation circuit adapted to receive a phase step factorsignal and being operable to generate a step phase value in response tothe first phase adjustment signal and the phase step factor signal, andwherein the first phase adjustment circuit is operable to subtract thestep phase value plus a value of the first phase adjustment signal fromthe first input sample of each symbol.
 9. The carrier tracking circuitof claim 8 wherein the first phase adjustment circuit is furtheroperable to incrementally increase the value subtracted from eachsubsequent input sample in a given symbol by the value of the firstphase adjustment signal.
 10. The carrier tracking circuit of claim 3wherein the first phase adjustment circuit further comprises anumerically controlled oscillator and wherein the second phaseadjustment circuit comprises a numerically-controlled oscillator. 11.The carrier tracking circuit of claim 3 wherein the delay elementcomprises a fast Fourier transform (FFT) element and wherein a group ofthe phase-corrected input samples correspond to a time domain sample ofan OFDM symbol, the FFT element being operable to generate as outputcomponents a group of frequency components for the OFDM symbol inresponse to the group of phase-corrected input samples.
 12. An OFDMreceiver, comprising: a radio frequency receiver circuit; ananalog-to-digital converter coupled to the radio frequency receivercircuit; a serial-to-parallel converter coupled to the analog-to-digitalconverter; an FFT circuit coupled to the serial-to-parallel converter; aparallel-to-serial converter coupled to the output of the FFT circuit; asymbol demodulation circuit; and a carrier tracking circuit coupled tothe analog-to-digital converter and to the parallel-to-serial converter,the carrier tracking circuit including, a first phase adjustment circuitcoupled to receive input samples from the analog-to-digital converterand operable to adjust a phase value of each input sample responsive toa first phase adjustment signal to thereby generate a correspondingphase-adjusted input sample, with groups of the input samplescorresponding to sequentially received OFDM symbols; a second phaseadjustment circuit coupled to the FFT circuit to receive outputcomponents from the FFT, the second phase adjustment circuit operable toadjust a phase value of each output component responsive to a secondphase adjustment signal to thereby generate phase-adjusted outputcomponents corresponding to a particular OFDM symbol; and a phasecorrection circuit coupled to the first and second phase adjustmentcircuits, the phase correction circuit operable to generate the firstphase adjustment signal having a value that is a function of the valuesof the phase-adjusted output components for a particular OFDM symbol,and operable to delay application of the phase adjustment signal to thefirst phase adjustment circuit for approximately a first delay time atwhich a first input sample of a subsequent OFDM symbol is applied to thefirst phase adjustment circuit, and the phase correction circuit furtheroperable to generate the second phase adjustment signal having a valuethat is equal to the value the first phase adjustment signal for asecond delay time and that is thereafter equal to a new value of thefirst phase adjustment signal associated with a subsequent OFDM symbolminus an initial value of the first phase adjustment signal associatedwith the prior OFDM symbol, the second delay time being equal toapproximately the time between when the initial value of the first phaseadjustment signal is generated and the time when the output componentsfor a subsequent OFDM symbol that have been phase adjusted using thatinitial value are output from the FFT.
 13. The OFDM receiver of claim 12wherein the phase correction circuit further comprises a feed forwardphase correction circuit coupled to the output of the second phaseadjustment circuit, the feed forward phase correction circuit operableto adjust the phase values of the phase adjusted output components for aparticular OFDM symbol using the first phase adjustment signal generatedfrom the phase adjusted output components of that OFDM symbol.
 14. TheOFDM receiver of claim 12 wherein the first phase adjustment circuit isfurther operable to incrementally increase the value subtracted fromeach subsequent input sample in a given OFDM symbol by the value of thefirst phase adjustment signal.
 15. The OFDM receiver of claim 12 whereinthe first and second phase adjustment circuits each include numericallycontrolled oscillators.
 16. The OFDM receiver of claim 12 wherein thesymbol demodulation circuit comprises a QAM demapping circuit.
 17. AnOFDM communications system, comprising: an OFDM transmitter operable tocommunicate a modulated OFDM signal over a wireless communicationschannel; and an OFDM receiver including, a radio frequency receivercircuit adapted to receive the modulated OFDM signal; ananalog-to-digital converter coupled to the radio frequency receivercircuit; a serial-to-parallel converter coupled to the analog-to-digitalconverter; an FFT circuit coupled to the serial-to-parallel converter; aparallel-to-serial converter coupled to the output of the FFT circuit; asymbol demodulation circuit; and a carrier tracking circuit coupled tothe analog-to-digital converter and to the parallel-to-serial converter,the carrier tracking circuit including, a first phase adjustment circuitcoupled to receive input samples from the analog-to-digital converterand operable to adjust a phase value of each input sample responsive toa first phase adjustment signal to thereby generate a correspondingphase-adjusted input sample, with groups of the input samplescorresponding to sequentially received OFDM symbols; a second phaseadjustment circuit coupled to the FFT circuit to receive outputcomponents from the FFT, the second phase adjustment circuit operable toadjust a phase value of each output component responsive to a secondphase adjustment signal to thereby generate phase-adjusted outputcomponents corresponding to a particular OFDM symbol; and a phasecorrection circuit coupled to the first and second phase adjustmentcircuits, the phase correction circuit operable to generate the firstphase adjustment signal having a value that is a function of the valuesof the phase-adjusted output components for a particular OFDM symbol,and operable to delay application of the phase adjustment signal to thefirst phase adjustment circuit for approximately a first delay time atwhich a first input sample of a subsequent OFDM symbol is applied to thefirst phase adjustment circuit, and the phase correction circuit furtheroperable to generate the second phase adjustment signal having a valuethat is equal to the value the first phase adjustment signal for asecond delay time and that is thereafter equal to a new value of thefirst phase adjustment signal associated with a subsequent OFDM symbolminus an initial value of the first phase adjustment signal associatedwith the prior OFDM symbol, the second delay time being equal toapproximately the time between when the initial value of the first phaseadjustment signal is generated and the time when the output componentsfor a subsequent OFDM symbol that have been phase adjusted using thatinitial value are output from the FFT.
 18. The OFDM communicationssystem of claim 17 wherein the phase correction circuit furthercomprises a feed forward phase correction circuit coupled to the outputof the second phase adjustment circuit, the feed forward phasecorrection circuit operable to adjust the phase values of the phaseadjusted output components for a particular OFDM symbol using the firstphase adjustment signal generated from the phase adjusted outputcomponents of that OFDM symbol.
 19. The OFDM communications system ofclaim 17 wherein the first phase adjustment circuit is further operableto incrementally increase the value subtracted from each subsequentinput sample in a given OFDM symbol by the value of the first phaseadjustment signal.
 20. The OFDM communications system of claim 17wherein the first and second phase adjustment circuits each includenumerically controlled oscillators.
 21. The OFDM communications systemof claim 17 wherein the symbol demodulation circuit comprises a QAMdemapping circuit.
 22. A method of correcting for frequency offset in acommunications system that communicates data symbols, the methodcomprising: generating a first group of frequency components thatcorrespond to a data symbol by applying an FFT algorithm to a group oftime domain input samples that correspond to the symbol; calculating aphase adjustment value from the group of frequency components; adjustingthe phase values of subsequent groups of time domain input samplescorresponding to subsequent symbols in using the calculated phaseadjustment value for a prior symbol, the phase values of the subsequenttime domain input samples being adjusted prior to applying the FFTalgorithm to these input samples; adjusting the phase values of thegroups of frequency components generated by the FFT algorithm for agiven symbol using the phase adjustment value calculated from thefrequency components of a prior symbol; when a given symbol has thephase values of the corresponding time domain input samples adjustedusing the phase adjustment value calculated from a particular priorsymbol, compensating for this adjustment to the time domain inputsamples when adjusting the phase values of the group of frequencycomponents corresponding to this given symbol; wherein each group oftime domain input samples includes r(1)-r(N) input samples; and whereinadjusting the phase values of subsequent groups of time domain inputsamples includes, subtracting a phase increment from the phase valuesfor each of the time domain input samples r(1)-r(N) in a group, thephase increment linearly increasing from the first input sample r(1) tothe last input sample r(N).
 23. The method of claim 22 whereinsubtracting a phase increment further comprises subtracting a step phasevalue from the first input sample r(1), the step phase value beingdetermined as function of the how each phase adjustment value iscalculated.
 24. The method of claim 23 wherein each phase adjustmentvalue is calculated to represent the average phase error correspondingapproximately to the phase error of the r(N/2) input sample, and thestep phase value is equal to N/2 plus an offset value plus anincremental value to be linearly applied to the input samples havingtheir phase values adjusted.
 25. The method of claim 22 whereincompensating for the adjustment to the time domain input samples when agiven symbol has the phase values of the corresponding time domain inputsamples adjusted using the phase adjustment values calculated from aparticular prior symbol comprises subtracting the phase adjustment valuegenerated from the particular prior symbol from a current phaseadjustment value and using the difference to adjust the phase values ofthe frequency components corresponding to the particular symbol whenthese components are output from the FFT.
 26. The method of claim 22wherein each symbol comprises an OFDM symbol.
 27. A method of correctingfor frequency offset in an OFDM communications system that communicatesOFDM symbols, each OFDM symbol including a plurality of correspondingtime domain input samples and a plurality of corresponding frequencycomponents generated by applying a frequency analysis algorithm to thetime domain input samples, each time domain input sample and eachfrequency component having an associated phase and magnitude, the methodcomprising: calculating a phase adjustment value from the frequencycomponents of each OFDM symbol; adjusting the phases of the time domaininput samples of at least one prior OFDM symbol using the calculatedphase adjustment value for a prior OFDM symbol prior to applying theinput samples to the frequency analysis algorithm; adjusting the phasesof the frequency components of at least one prior OFDM symbol using thecalculate phase adjustment value for a prior OFDM symbol; and adjustingthe phases of the frequency components of a given OFDM symbol using thecalculated phase adjustment value for that OFDM symbol; whereinadjusting the phases of the frequency components of a given OFDM symbolusing the calculated phase adjustment value for that OFDM symbolcomprises: multiplying the calculated phase adjustment value by a feedforward scale factor to generate a feed forward offset value; andsubtracting the feed forward offset value from each of the frequencycomponents of the given OFDM symbol.
 28. The method of claim 27 whereinadjusting the phases of the time domain input samples of a given OFDMsymbol comprises subtracting a linearly increasing phase increment fromeach of the input samples.
 29. The method of claim 28 wherein the phaseof the first sample of the OFDM symbol is further adjusted bysubtracting a step phase value.
 30. The method of claim 29 wherein thestep phase value is calculated using one half the number of inputsamples for each OFDM symbol plus an offset value determined by thenumber of cyclic prefix samples in the OFDM symbol.
 31. A methodcomprising: generating a first phase offset value for a multicarrierframe and a subsequent first phase offset value for a subsequentmulticarrier frame, wherein the first phase offset value and thesubsequent first phase offset value are representative of an averagephase offset of the multicarrier frame and the subsequent multicarrierframe, and wherein the first phase offset value and the subsequent firstphase offset value are generated with a phase estimation circuit;determining a step phase offset that accumulates during reception of themulticarrier frame, wherein the step phase offset is determined with astep phase compensation circuit; applying a first corrected phase offsetto a set of time-domain input samples of the multicarrier frame with afirst summation circuit to create a set of phase-corrected time-domainsamples, wherein the first corrected phase offset includes the firstphase offset value and the step phase offset; converting the set ofphase-corrected time-domain samples to a set of frequency domain sampleswith a frequency transform; applying a second phase offset value to theset of frequency domain samples with a second summation circuit, whereinthe second phase offset value is based on the first phase offset valueand the subsequent first phase offset value.
 32. The method of claim 31wherein applying the first corrected phase offset comprises subtractinga linearly increasing phase increment from each of the set oftime-domain input samples.
 33. The method of claim 31 wherein the stepphase offset is calculated using one half the number of input samplesfor each symbol plus an offset value determined by the number of cyclicprefix samples in the symbol.
 34. An apparatus comprising: a phase errorestimator configured to generate a first phase offset value for amulticarrier frame based on pilot tones, wherein the first phase offsetvalue represents an average phase offset, and wherein the phase errorestimator is further configured to determine a subsequent first phaseoffset value; a first numerically controlled oscillator configured todetermine a step phase offset that accumulates during reception of themulticarrier frame and to apply a first corrected phase offset to a setof time-domain input samples of the multicarrier frame to create a setof phase-corrected time-domain samples, wherein the first correctedphase offset includes the first phase offset value and the step phaseoffset; a delay element configured to convert the set of phase-correctedtime-domain samples to a set of frequency domain samples with afrequency transform; and a second numerically controlled oscillatorconfigured to apply a second phase offset value to the set of frequencydomain samples, wherein the second phase offset value is based on thefirst phase offset value and the subsequent first phase offset value.35. The apparatus of claim 34 further comprising a feed forward phasecorrection circuit configured to adjust phase values of phase adjustedoutput components for a particular OFDM symbol using a first phaseadjustment signal generated from the phase error estimator.
 36. Theapparatus of claim 34 wherein the first numerically controlledoscillator is further configured to incrementally increase a valuesubtracted from each subsequent input sample in a given OFDM symbol bythe value of a first phase adjustment signal.
 37. The apparatus of claim34 further comprising a symbol demodulation circuit configured to dempapa QAM symbol.
 38. A carrier tracking circuit, comprising: a first phaseadjustment circuit configured to: receive input samples; adjust a phasevalue of each of the input samples responsive to a first phaseadjustment signal; and generate corresponding phase-adjusted inputsamples; a delay element configured to generate a group of outputcomponents responsive to a group of the phase-adjusted input samples; asecond phase adjustment circuit configured to adjust a phase value ofeach output component of the group of output components responsive to asecond phase adjustment signal to generate phase adjusted outputcomponents; a phase correction circuit configured to: generate anestimated phase adjustment signal having a value that is a function ofvalues of the phase-adjusted output components; generate the first phaseadjustment signal based on the estimated phase adjustment signal; delayapplication of the first phase adjustment signal to the first phaseadjustment circuit for approximately a first delay time; and generatethe second phase adjustment signal having a value that is equal to avalue of the estimated phase adjustment signal for a second delay time;and a feed forward phase correction circuit configured to adjust phasevalues of phase adjusted output components for a particular OFDM symbolusing the first phase adjustment signal.
 39. The carrier trackingcircuit of claim 38 wherein the feed forward phase correction circuit isfurther configured to generate a feed forward offset phase bymultiplying the first phase adjustment signal by a feed forward scalefactor, and subtract the feed forward offset phase from the phaseadjusted output components.
 40. The carrier tracking circuit of claim 39wherein the feed forward scale factor is less than one.
 41. The carriertracking circuit of claim 40 wherein the feed forward phase correctioncircuit comprises: a summation circuit configured to subtract the feedforward offset phase from phase values of the output components toprovide output feed forward phase adjusted output components; and amultiplier operable to multiply the first phase adjustment signal by thefeed forward scale factor to provide the feed forward offset phase tothe summation circuit.
 42. The carrier tracking circuit of claim 38wherein the first phase adjustment circuit comprises a step phasecompensation circuit configured to receive a phase step factor signaland generate a step phase value in response to the first phaseadjustment signal and the phase step factor signal, and wherein thefirst phase adjustment circuit is configured to subtract the step phasevalue plus a value of the first phase adjustment signal from a firstinput sample of a symbol.
 43. The carrier tracking circuit of claim 42wherein the first phase adjustment circuit is further configured toincrementally increase a value subtracted from a subsequent input samplein a given symbol by the value of the first phase adjustment signal. 44.The carrier tracking circuit of claim 38 wherein the first phaseadjustment circuit further comprises a numerically controlled oscillatorand wherein the second phase-adjustment circuit comprises anumerically-controlled oscillator.
 45. The carrier tracking circuit ofclaim 38 wherein the delay element comprises a fast Fourier transform(FFT) element configured to generate as output components a group offrequency components for an OFDM symbol in response to the group ofphase-adjusted input samples.
 46. A method comprising: generating afirst group of frequency components that correspond to a data symbol;calculating a phase adjustment value from the first group of frequencycomponents with a phase estimation circuit; adjusting phase values ofsubsequent groups of time domain input samples corresponding tosubsequent symbols with a first phase correction circuit based on thephase adjustment value; adjusting phase values of the first group offrequency components with a second phase correction circuit based on aphase adjustment value calculated from frequency components of a priorsymbol, wherein the frequency components are calculated with a frequencytransform; compensating for the adjusting of phase values of the firstgroup of frequency components; wherein the subsequent groups of timedomain input samples include r(1)-r(N) input samples, and whereinadjusting the phase values of the subsequent groups of time domain inputsamples includes subtracting a phase increment from phase values foreach of the input samples r(1)-r(N), wherein the phase incrementlinearly increases from a first input sample r(1) to a last input sampler(N).
 47. The method of claim 46 wherein subtracting the phase incrementfurther comprises subtracting a step phase value from the first inputsample r(1), wherein the step phase value is determined based on how aphase adjustment value is calculated.
 48. The method of claim 47 whereinthe phase adjustment value is calculated to represent an average phaseerror corresponding approximately to a phase error of a r(N/2) inputsample, and the step phase value is equal to N/2 plus an offset valueplus an incremental value to be linearly applied to the input sampleshaving their phase values adjusted.
 49. The method of claim 46 whereincompensating for the adjusting of the phase values comprises subtractinga phase adjustment value generated from a particular prior symbol from acurrent phase adjustment value and using the difference to adjust thephase values of the first group of frequency components.
 50. The methodof claim 46 wherein the data symbol comprises an OFDM symbol.
 51. Anapparatus comprising: a phase error estimation means for generating afirst phase offset value for a multicarrier frame and a subsequent firstphase offset value for a subsequent multicarrier frame, wherein thefirst phase offset value and the subsequent first phase offset value arerepresentative of an average phase offset of the multicarrier frame andthe subsequent multicarrier frame; a first oscillator means fordetermining a step phase offset that accumulates during reception of themulticarrier frame and applying a first corrected phase offset to a setof time-domain input samples of the multicarrier frame to create a setof phase-corrected time-domain samples, wherein the first correctedphase offset includes the first phase offset value and the step phaseoffset; a delay means for converting the set of phase-correctedtime-domain samples to a set of frequency domain samples with afrequency transform; and a second oscillator means configured to apply asecond phase offset value to the set of frequency domain samples,wherein the second phase offset value is based on the first phase offsetvalue and the subsequent first phase offset value.
 52. The apparatus ofclaim 51 further comprising a feed forward phase correction means foradjusting phase values of phase adjusted frequency domain samples for aparticular OFDM symbol using a first phase adjustment signal.
 53. Theapparatus of claim 52 further comprising a means for incrementallyincreasing a value subtracted from each subsequent input sample in agiven OFDM symbol by the value of the first phase adjustment signal. 54.The apparatus of claim 51 further comprising a symbol demodulation meansfor demapping QAM symbols.